Nicky Lu, Ph.D., IEEE Fellow, NAE (USA) Member
Chairman, CEO & Founder, Etron Technology, Inc.

As a researcher, design architect, entrepreneur and chief executive, Dr. Nicky Lu has dedicated his career to the worldwide IC design and semiconductor industry. He also co-founded several other high-tech companies including Ardentec, Global Unichip and GTBF Corporations.

Dr. Lu worked for the IBM Research Division and then the Headquarters from 1982 to 1990 and won numerous IBM recognition awards, including an IBM Corporate Award. He co-invented and pioneered a 3D-DRAM technology, known as the Substrate-Plate Trench-Capacitor (SPT) cell, along with its associated array architecture, which has been widely used by IBM and its licensees from 4Mb to 1Gb DRAMs and embedded DRAMs over hundreds of billions dollars.

Dr. Lu designed several High-Speed CMOS DRAM (HSDRAM) chips, with all top world’s records of performance. He was a co-architect leading the 8-inch wafer and DRAM/SRAM/LOGIC technology developments for Taiwan semiconductor industry in early 1990s, also creating many Taiwan companies as prominent silicon-chip suppliers. Since 1999, he has pioneered Known-Good-Die Memory Products enabling 3D stacked-dices system chips; this work summoned the new rise of an IC Heterogeneous Integration Era as described in his ISSCC-2004 plenary talk, demonstrating a new 3D-IC trend. He was a keynote speaker at the 2016 A-SSCC (IEEE Asian Solid-State Circuits Conference) disclosing Silicon-Age-4.0 Era with a new Virtual Moore’s Law as an indicator of continual economic growth.

Dr. Lu received his B.S. in Electrical Engineering from National Taiwan University and M.S. and Ph.D. in EE from Stanford University. He holds over 30 U.S. patents and has published more than 60 technical papers. He serves as Managing Board Director and was Chairman of TSIA (Taiwan Semiconductor Industry Association), as Board Member of Global Semiconductor Alliance (GSA) and GSA’s General Chair (2009 to 2011), and Chairman of WSC (World Semiconductor Council) from 2014 to 2015.

He received the Scientific Management Award (2012) from Chinese Society for Management of Technology and Taiwan’s Golden Merchant Award (2007) from General Chamber of Commerce. He is an Outstanding Alumnus of National Taiwan University, a Chair Professor and an Outstanding Alumnus of National Chiao Tung University, an IEEE Fellow, the recipient of the IEEE 1998 Solid-States Circuits Award, a member of NAE (National Academy of Engineering of USA), and received of a SEMI Industry Contribution Award in 2017.

• As a Researcher, Design Architect and Chief Executive, Dr. Lu Has Dedicated His Career to the Worldwide IC Design and Semiconductor Industry

• A Serial Entrepreneur to Create/Lead with Partners Several Successful Semiconductor Companies (Etron, Ardentec Corp., Global Unichip Corp., etc.) Translating Technology Innovations to Real-World Impact and Economic Successes

• Chairman (2013-17) & Board Director (1998-Now) of TSIA (Taiwan Semiconductor Industry Association)

• Chairman (2014-15) of WSC (World Semiconductor Council)

• Chairman (2009-11) and Board Director (2004-Now) of GSA (Global Semiconductor Alliance)

• BSEE, National Taiwan University, MSEE/PhD, Stanford U.; Authored over 60 papers and 30 US Patents

• Member, National Academy of Engineering of USA; IEEE Fellow; IEEE 1998 Solid-State Circuits Award Recipient; Scientific Management Award (2012), Chinese Society for Management of Technology; Golden Merchant Award (2007), General Chamber of Commerce of R.O.C.

• Distinguished Alumnus, National Chiao Tung University (1998) & National Taiwan University (2011), Respectively; Associate Professor & Chair Professor, National Chiao Tung University (1981-1982 & 2005-2008)

• Invented/Realized the Most Dense SPT Trench DRAM Cell (1985) and Designed the World’s Fastest High-Speed DRAM Chip (1987) in IBM Research and as Program Manager in IBM Headquarters; Received the Corporate Highest-Honor Award (1990)

• Recipient of the 2001 National Medal of Excellence in Science & Technology in Taiwan for Pioneering National Submicron Project’s 8”-wafer advanced Technology, IC Designs and Architected a Fabless-Foundry-Subsystem Infrastructure in Taiwan

• Pioneer KGD Memories (Known-Good-Die DRAMs) to open a Silicon Era of Heterogeneous Integration (Recognized by Intel Supplier Award 2003 and 2004 ISSCC Keynote Speech) and Further Disclosed the Silicon Age 4.0 Direction with Both Function and Value-driven Scaling-up & down Methodologies for Future Silicon Industry Growth